OFDM demodulator

ABSTRACT

An OFDM demodulator includes an FFT circuit, a phase correction circuit, and a timing synchronization circuit. The timing synchronization circuit includes a symbol-boundary calculation circuit to estimate a symbol-boundary position Nx by filtering the correlation peak of a guard interval, symbol-boundary correction circuit to calculate a clock-phase error based on the symbol-boundary position Nx, and a start-flag generation circuit to generate a start flag for the FFT calculation. The symbol-boundary correction circuit subtracts only a value whose precision is smaller than the cycle of a reference clock from the symbol-boundary position Nx, and generates a phase correction signal for each sub-carrier based on the value. The phase correction circuit performs a complex multiplication of the FFF-calculated signal by the phase correction signal to correct the clock-phase error.

TECHNICAL FIELD

The present invention relates to a demodulator destined for demodulationof OFDM (orthogonal frequency division multiplex) modulated signal.

This application claims the priority of the Japanese Patent ApplicationNo. 2002-382214 filed on Dec. 27, 2002, the entirety of which isincorporated by reference herein.

BACKGROUND ART

For transmission of digital signals, there is available a modulationtechnique called “OFDM” (orthogonal frequency division multiplex). TheOFDM technique is such that data is digitally modulated for transmissionby dividing a transmission frequency band into many orthogonalsub-carriers and assigning the data to the amplitude and phase of eachof the sub-carriers by the phase shift keying (PSK) and quadratureamplitude modulation (QAM).

The OFDM technique is characterized in that since a transmissionfrequency band is divided into many sub-carriers, so the band persub-carrier is narrower and the modulation rate is lower, while thetransmission rate is not totally so different from that in theconventional modulation technique. The OFDM technique is alsocharacterized in that since many sub-carriers are transmitted inparallel, so the symbol rate is lower and the time length of a multipathin relation to that of a symbol can be reduced so that the OFDMtechnique will not easily be affected by the multipath fading.

Also, the OFDM technique is characterized in that since data is assignedto a plurality of sub-carriers, so a transmission/reception circuit canbe formed from an inverse fast Fourier transform (IFFT) calculationcircuit in order to modulate the data, while it can be formed from afast Fourier transform (FFT) calculation circuit in order to demodulatethe modulated data.

Because of the above-mentioned characteristics, the OFDM technique isfrequently applied to the digital terrestrial broadcasting which iscritically affected by the multipath fading. To the digital terrestrialbroadcasting adopting the OFDM technique, there is applied the DigitalVideo Broadcasting-Terrestrial (DVB-T) standard, Integrated ServicesDigital Broadcasting-Terrestrial (ISDB-T) standard or the like, forexample.

As shown in FIG. 1, the transmission symbol used in the OFDM technique(will be referred to as “OFDM symbol” hereunder) is formed from aneffective symbol as a signal duration for which IFFT is effected fortransmission of data, and a guard interval as a copy of the waveform ofan end portion of the effective symbol. The guard interval is providedin the leading portion of the OFDM symbol. Owing to such a guardinterval, the OFDM technique allows a multipath-caused inter-symbolfading and improves the multipath resistance.

In the mode 3 of the ISDB-T_(SB) standard (broadcasting standard for thedigital terrestrial broadcasting, adopted in Japan), the effectivesymbol includes 512 sub-carriers spaced 125/126 kHz (≈0.992 kHz) fromone to a next one. Also in the mode 3 of the ISDB-T_(SB) standard,transmission data is modulated to 433 of the 512 sub-carriers in theeffective symbol. Further in the mode 3 of the ISDB-TSB standard, thelength of time of the guard interval is ¼, ⅛, 1/16 or 1/32 of that ofthe effective symbol.

A conventional OFDM receiver will be illustrated and described.

FIG. 2 schematically illustrates the conventional OFDM receiver in theform of a block diagram.

As shown in FIG. 2, the conventional OFDM receiver, generally indicatedwith a reference 100, includes an antenna 101, tuner 102, band-passfilter (BPF) 103, A-D conversion circuit 104, DC canceling circuit 105,digital orthogonal demodulation circuit 106, FFT calculation circuit107, frame extraction circuit 108, synchronization circuit 109, carrierdemodulation circuit 110, frequency deinterleaving circuit 111, timedeinterleaving circuit 112, demapping circuit 113, bit deinterleavingcircuit 114, depuncture circuit 115, Viterbi circuit 116, bytedeinterleaving circuit 117, spread-signal canceling circuit 118,transport stream generation circuit 119, RS decoding circuit 120,transmission-control information decoding circuit 121, and a channelselection circuit 122.

A transmission wave sent from a broadcast station is received by theantenna 101 of the OFDM receiver 100 and supplied as an RF signal to thetuner 102.

The RF signal received by the antenna 101 is converted in frequency bythe tuner 102 composed of a multiplier 102 a and local oscillator 102 binto an IF signal, and the IF signal is supplied to the BPF 103. Theoscillation frequency of a reception carrier signal generated by thelocal oscillator 102 b is changed correspondingly to a channel selectfrequency supplied from the channel selection circuit 122.

The IF signal from the tuner 102 is filtered by the BPF 103, and thendigitized by the A-D conversion circuit 104. The digital IF signal thusproduced has the DC component thereof canceled by the DC cancelingcircuit 105, and is supplied to the digital orthogonal demodulationcircuit 106.

The digital orthogonal demodulation circuit 106 makes orthogonaldemodulation of the digital IF signal with the use of a carrier signalof a predetermined frequency (carrier frequency) to provide a basebandOFDM signal. The orthogonal demodulation of the baseband OFDM signalprovides a complex signal composed of a real-axis component (I-channelsignal) and an imaginary-axis signal (Q-channel signal). The basebandOFDM signal from the digital orthogonal demodulation circuit 106 issupplied to the FFT calculation circuit 107 and synchronization circuit109.

The FFT calculation circuit 107 makes FFT calculation of the basebandOFDM signal to extract a signal having been orthogonal-modulated to eachsub-carrier, and provides it as an output.

The FFT calculation circuit 107 extracts a signal having an effectivesymbol length from one OFDM symbol and makes FFT calculation of theextracted signal. More specifically, the FFT calculation circuit 107removes a signal having a guard interval length from one OFDM symbol,and makes FT calculation of the residual of the OFDM symbol. Signals forFFT calculation may be extracted from any arbitrary positions in oneOFDM symbol if the signal extraction points are consecutive. Namely, thesignal extraction will start at any position in a range from the leadingboundary of the OFDM symbol (indicated with a reference A in FIG. 1) tothe end of the guard interval (indicated with a reference B in FIG. 1)as shown in FIG. 1.

A signal extracted by the FFT calculation circuit 107 and having beenmodulated to each sub-carrier is a complex signal composed of areal-axis component (I-channel signal) and an imaginary-axis component(Q-channel signal). The signal extracted by the FFT calculation circuit107 is supplied to the frame extraction circuit 108, synchronizationcircuit 109 and carrier demodulation circuit 110.

Based on the signal demodulated by the FFT calculation circuit 107, theframe extraction circuit 108 extracts boundaries of an OFDM transmissionframe, while demodulating pilot signals such as CP, SP, etc. included inthe OFDM transmission frame and transmission-control information such asTMCC, TPS, etc., and supplies the demodulated pilot signals andtransmission-control information to the synchronization circuit 109 andtransmission-control information demodulation circuit 121.

Using the base-band OFDM signal, signals having been modulated to thesub-carriers after demodulated by the FFT calculation circuit 107, pilotsignals such as CP, SP, etc. detected by the frame extraction circuit108 and channel select signal supplied from the channel selectioncircuit 122, the synchronization circuit 109 calculates boundaries ofthe OFDM symbol, and sets an FFT-calculation start timing for the FFTcalculation circuit 107.

The carrier demodulation circuit 110 is supplied with signalsdemodulated from the sub-carrier outputs from the FFT calculationcircuit 107, and makes carrier demodulation of the supplied signal. Fordemodulation of an ISDB-T_(SB)-based OFDM signal, for example, thecarrier demodulation circuit 110 will makes differential demodulation ofthe signal by the DQPSK technique or synchronous demodulation by theQPSK, 16QAM or 64QAM technique.

The carrier-demodulated signal undergoes frequency-directionaldeinterleaving by the frequency deinterleaving circuit 111, thentime-directional deinterleaving by the time deinterleaving circuit 112,and is supplied o the demapping circuit 113.

The demapping circuit 113 makes demapping of the carrier-demodulatedsignal (complex signal) to restore the transmission data series. Fordemodulation of an ISDB-T_(SB)-based OFDM signal, for example, thedemapping circuit 113 will make demapping corresponding to the QPSK,16QAM or 64QAM technique.

Being passed through the bit deinterleaving circuit 114, depuncturecircuit 115, Viterbi circuit 116, byte deinterleaving circuit 117 andspread-signal canceling circuit 118, the transmission data series outputfrom the demapping circuit 113 undergoes deinterleaving corresponding toa bit deinterleaving for distribution of a multi-valued symbol error,puncturing for reduction of transmission bits, Viterbi decoding fordecoding a convolution-encoded bit string, deinterleaving in bytes, andenergy despreading corresponding to the energy spreading, and thetransmission data series thus processed is supplied to the transportstream generation circuit 119.

The transport stream generation circuit 119 inserts data defined by eachbroadcasting technique, such as null packet, in a predetermined positionin a data stream. Also, the transport stream generation circuit 119“smoothes” bit spaces in an intermittently supplied data stream toprovide a temporally continuous stream. The transmission data seriesthus smoothed is supplied to the RS decoding circuit 120.

The RS decoding circuit 120 makes Reed-Solomon decoding of the suppliedtransmission data series, and provides the transmission data series thusdecoded as a transport stream defined in the MPEG-2 Systems.

The transmission-control information decoding circuit 121 decodestransmission-control information having been modulated in apredetermined position in the OFDM transmission frame, such as TMCC orTPS. The decoded transmission-control information is supplied to thecarrier demodulation circuit 110, time deinterleaving circuit 112,demapping circuit 113, bit deinterleaving circuit 114 and transportstream generation circuit 119, and used to control the demodulation,reproduction, etc. effected in these circuits.

Note here that for demodulation of an OFDM signal, it is necessary tocorrectly detect boundaries of the OFDM symbol and make FFT calculationsynchronously with the boundary positions. The correct detection ofboundary positions of an OFDM symbol for synchronization of the ODFMsymbols is called “symbol synchronization”.

The boundary position of an OFDM symbol is not always coincident withthe operation clock for the receiver. The start timing of the FFTcalculation can only be controlled in units of the operation clock forthe receiver. On this account, even if a boundary position has beencalculated accurately with OFDM symbols being synchronized with eachother, FFT calculation will result in an error whose precision issmaller than the cycle of the operation clock of the OFDM signal, asshown in FIG. 3.

The error smaller than the operation clock cycle can be canceled bysynchronizing the operation clocks by means of a clock reproductioncircuit such as a PLL, for example. For example, in a receiver in whichno operation-clock PLL is done of a received OFDM signal, however, thecanceling of the error is extremely complicated. To cancel an errorsmaller than the operation clock cycle, it has been proposed tocalculate a phase rotation of a pilot signal, which however will lead toa slower synchronization pull-in and to a complicated circuit.

DISCLOSURE OF THE INVENTION

Accordingly, the present invention has an object to overcome theabove-mentioned drawbacks of the related art by providing a simplyconstructed OFDM demodulator capable of a high-speed, high-accuracycorrection of a difference of less than the operation clock cyclebetween an extraction position for Fourier transform and a boundaryposition of a received transmission.

The above object can be attained by providing an OFDM demodulator fordemodulating an orthogonal frequency division multiplex (OFDM) signalwhose unit of transmission is a transmission symbol including effectivesymbols generated by making time division of an information series andmodulating the information into a plurality of sub-carriers and a guardinterval generated by copying the signal waveform of a part of theeffective symbols, the apparatus including, according to the presentinvention, a reference time generating circuit for generating areference time on the basis of a reference clock; a Fourier transformcircuit for extracting a complex signal modulated in each sub-carrier ofthe transmission symbol by extracting signal areas corresponding to thenumber of sub-carriers for the effective symbols of the OFDM signalsampled with the reference clock and making Fourier transform of theextracted signal areas; a guard correlation peak time detecting circuitfor detecting a timing in which the autocorrelation of the guardinterval portion of the OFDM signal attains to its peak and generatingthe timing (peak time) synchronous with the reference time; asymbol-boundary time estimating circuit for estimating, on the basis ofthe peak time, a symbol-boundary time that is a boundary time of thetransmission symbol synchronous with the reference time; a timingcontrol circuit for controlling the timing position where the signal areextracted by the Fourier transform circuit on the basis of thesymbol-boundary time represented by the precision of the reference clockcycle; and a phase correcting circuit for calculating a phase-correctionamount on the basis of the symbol-boundary time represented by aprecision smaller than the reference clock cycle and making, on thebasis of the calculated phase-correction amount, phase correction of thecomplex signal having been modulated in each sub-carrier and extractedby the Fourier transform circuit.

The above OFDM demodulator according to the present invention is verysimply constructed without using any clock reproduction circuit such asPLL and phase-rotation detection circuit using a pilot signal, and cancorrect a difference whose precision is smaller than the operation clockcycle between the extraction position for the Fourier transform andboundary position of the received transmission symbol with a higherpull-in speed and higher precision.

These objects and other objects, features and advantages of the presentinvention will become more apparent from the following detaileddescription of the best mode for carrying out the present invention whentaken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 explains the transmission symbol used in the OFDM technique.

FIG. 2 is a block diagram of the conventional OFDM receiver.

FIG. 3 explains a positional shift of a start flag indicating a startposition of the FFT calculation from an OFDM symbol-boundary position.

FIG. 4 is a block diagram of an OFDM receiver as an embodiment of thepresent invention.

FIG. 5 shows the construction of an FFT calculation circuit.

FIG. 6 is a block diagram of a guard correlation/peak detection circuit.

FIG. 7 is a timing diagram of each signal in the guard correlation/peakdetection circuit.

FIG. 8 is a block diagram of a timing synchronization circuit.

FIG. 9 is a block diagram of a symbol-boundary calculation circuit.

FIG. 10 is a circuit diagram of a phase comparison circuit included inthe symbol-boundary calculation circuit.

FIG. 11 is a circuit diagram of a limiter included in thesymbol-boundary calculation circuit.

FIG. 12 is a circuit diagram of an asymmetric gain circuit included inthe symbol-boundary calculation circuit.

FIG. 13 is a circuit diagram of a low-pass filter included in thesymbol-boundary calculation circuit.

FIG. 14 is a circuit diagram of a clock-frequency error calculationcircuit included in the timing synchronization circuit.

FIG. 15 is a circuit diagram of a phase generation circuit included inthe symbol-boundary calculation circuit.

FIG. 16 is a circuit diagram of a symbol-boundary correction circuit andstart-flag generation circuit.

FIG. 17 shows sub-carrier numbers.

BEST MODE FOR CARRYING OUT THE INVENTION

The present invention will be described in detail below concerning theOFDM receiver as an embodiment thereof.

Overview of the OFDM Receiver

FIG. 4 is a block diagram of the OFDM receiver as an embodiment of thepresent invention.

As show in FIG. 4, the OFDM receiver, generally indicated with areference 1, as the embodiment of the present invention includes anantenna 2, tuner 3, band-pass filter (BPF) 4, A-D conversion circuit 5,clock generation circuit 6, DC canceling circuit 7, digital orthogonaldemodulation circuit 8, carrier-frequency error correction circuit 9,FFT calculation circuit 10, phase correction circuit 11, guardcorrelation/peak detection circuit 12, timing synchronization circuit13, narrow-band carrier error calculation circuit 14, wide-band carriererror calculation circuit 15, addition circuit 16, numerical-controloscillation (NCO) circuit 17, frame synchronization circuit 18,equalization circuit 19, demapping circuit 20, transmission-channeldecoding circuit 21, and a transmission-control information decodingcircuit 22.

Digital broadcast waves from a broadcast station are received by theantenna 2 of the OFDM receiver 1, and supplied as a RF signal to thetuner 3.

The RF signal received by the antenna 2 is converted in frequency to anIF signal by the tuner 3 including the multiplier 3 a and localoscillator 3 b, and supplied to the BPF 4. The IF signal output from thetuner 3 is filtered by the BPF 4 and then supplied to the A-D conversioncircuit 5.

The A-D conversion circuit 5 samples the IF signal with a clock suppliedfrom the clock generation circuit 6, and digitizes the IF signal. The IFsignal thus digitized by the A-D conversion circuit 5 is supplied to theDC canceling circuit 7 where it will have the DC component thereofcanceled, and the signal is supplied to the digital orthogonaldemodulation circuit 8. The digital orthogonal demodulation circuit 8makes orthogonal demodulation of the digital IF signal with the use of atwo-phase carrier signal of a predetermined carrier frequency, andprovides a base-band OFDM signal as an output. An OFDM time-domainsignal output from the digital orthogonal demodulation circuit 8 issupplied to the carrier-frequency error correction circuit 9.

Note here that for the digital orthogonal demodulation, the digitalorthogonal demodulation circuit 8 needs a two-phase signal having a −Sincomponent and Cos component as a carrier signal. On this account, in theOFDM receiver 1, the frequency of the sampling clock supplied to the A-Dconversion circuit 5 is made four times higher than the center frequencyf_(1F) of the IF signal to generate a two-phase carrier signal forsupply to the digital orthogonal demodulation circuit 8.

Also, in the OFDM receiver 1, after completion of the digital orthogonaldemodulation, a data series of a clock of 4f_(1F) is down-sampled to 1/4to equalize the number of samples of the effective symbol havingundergone the digital orthogonal demodulation to the number (Nu) ofsub-carriers. That is, the clock for the data series subjected to thedigital orthogonal demodulation has a frequency that is 1/sub-carrierspace. Also, the down-sampling rate after the digital orthogonaldemodulation may be ½ to make FFT calculation with the number ofsamples, double the normal one, and the data series be furtherdown-sampled to ½ after completion of the FFT calculation. By making theFFT calculation with the number of samples, double the normal one, it ispossible to extract, by the FFT calculation, a signal in a two-timewider frequency band and thus reduce the circuit scale of the low-passfilter circuit for the digital orthogonal demodulation. It should benoted that for each of the downstream circuits to process theover-sampled data series, the number (Nu) of samples of the effectivesymbol having undergone the digital orthogonal demodulation may be 2^(n)times (n is a natural number) larger than the number of sub-carriers.

The clock generation circuit 6 supplies the A-D conversion circuit 5with a clock of the aforementioned frequency, and each of the circuitsof the OFDM receiver 1 with an operation clock for the data serieshaving undergone the digital orthogonal demodulation (a clock of afrequency equal to a quarter of the frequency of the clock for supply tothe A-D conversion circuit 5, for example, a clock of a frequency equalto 1/sub-carrier space).

Note that the operation clock generated by the clock generation circuit6 is a free-running clock not synchronous with a transmission clock forthe received OFDM signal. That is, the operation clock from the clockgeneration circuit 6 free-runs without synchronization in frequency andphase with the transmission clock by PLL or the like. The operationclock can free-run because the timing synchronization circuit 13 detectsa frequency error between the OFDM signal transmission clock and theoperation clock, and cancels the frequency error on the basis of thefrequency error component by a feed-forwarding made in the systemdownstream of the timing synchronization circuit 13. Although in thisOFDM receiver 1, the clock generation circuit 6 generates anasynchronous free-running clock as above, the present invention isapplicable to a device that can vary the operation flock frequency by afeedback control.

Also, the base-band OFDM signal output from the digital orthogonaldemodulation circuit 8 is a so-called time-domain signal not yet subjectto FFT calculation. Thus, the yet-to-FFT-calculated baseband signal willbe referred to as “OFDM time-domain signal” hereunder. The OFDMtime-domain signal is orthogonal-demodulated to provide a complex signalcomposed of a real-axis component (I-channel signal) and animaginary-axis component (Q-channel signal).

The carrier-frequency error correction circuit 9 makes complexmultiplication of a carrier-frequency error correction signal outputfrom the NCO 17 by the OFDM time-domain signal having undergone thedigital orthogonal demodulation to correct a carrier-frequency error ofthe OFDM time-domain signal. The OFDM time-domain signal having thecarrier-frequency error thereof corrected by the carrier-frequency errorcorrection circuit 9 is supplied to the FFT calculation circuit 10 andguard correlation/peak detection circuit 12.

The FFT calculation circuit 10 makes FFT calculation of the number (Nu)of samples of the effective symbol by extracting a signal having theeffective symbol length from one OFDM symbol, that is, extracting asignal resulted from canceling of the number (Ng) of samples of a guardinterval from the total number (Ns) of samples of the one OFDM symbol.The FFT calculation circuit 10 is supplied with the start flag (starttiming of the FFT calculation) which identifies a range of extractionfrom the timing synchronization circuit 13, and makes FFT calculation intiming of the start flag.

As shown in FIG. 5, the FFT calculation circuit 10 includes aserial-parallel conversion circuit 25, guard interval canceller 26, FFTcalculator 27, and a parallel-serial conversion circuit 28, for example.

The serial-parallel converter 25 starts counting at a start flagsupplied from the timing synchronization circuit 13, extracts data forthe number (Ns) of samples of the OFDM symbol, and outputs parallel datawhose one word is Ns. The guard interval canceller 26 allows the top Nudata of the parallel data whose one word is Ns samples to pass bywithout outputting the Ng data next to the word. The FFT calculator 27make FFT calculation of data for the number (Nu) of samples of theeffective symbol supplied from the guard interval canceller 26. Theparallel-serial converter 28 is supplied with data for the number (Nu)of sub-carriers from the FFT calculator 27. The parallel-serialconverter 28 outputs the Nu data after serializing the latter.

The FFT calculation circuit 10 extracts a signal component having beenmodulated in sub-carriers in one OFDM symbol by extracting data for thenumber of samples in the effective symbol from the OFDM symbol andmaking FFT calculation of the data.

The signal output from the FFT calculation circuit 10 is a so-calledfrequency-domain signal having undergone the FFT calculation. Thus, theFFT-calculated signal will be referred to as “OFDM frequency-domainsignal” hereunder. Also, the OFDM frequency-domain signal output fromthe FFT calculation circuit 10 is a complex signal composed of areal-axis component (I-channel signal) and imaginary-axis signal(Q-channel signal) similarly to the OFDM time-domain signal. The OFDMfrequency-domain signal is supplied to the phase correction circuit 11.

The phase correction circuit 11 corrects a phase-rotated component thatwill be caused in the OFDM frequency-domain signal by a shift of anactual boundary position of an OFDM symbol from the start timing of theFFT calculation. The phase correction circuit 11 corrects a phase shiftcaused with a precision smaller than the sampling cycle. Morespecifically, the phase correction circuit 11 corrects a phase rotationof the PFDM frequency-domain signal output from the FFT calculationcircuit 10 by making complex multiplication of a phase correction signal(complex signal) supplied from the timing synchronization circuit 13.The OFDM frequency-domain signal corrected in phase rotation is suppliedto the wideband carrier error calculation circuit 15, framesynchronization circuit 18, equalization circuit 19 andtransmission-control information decoding circuit 22.

The guard correlation/peak detection circuit 12 is supplied with theOFDM time-domain signal. The guard correlation/peak detection circuit 12will determine the value of a correlation between the supplied OFDMtime-domain signal and OFDM time-domain signal delayed by the effectivesymbol. It should be noted here that the length of time for which thecorrelation is to be determined is set to the length of the guardinterval time.

Thus, the signal indicating the correlation value (will be referred toas “guard correlation signal” hereunder) has a peak precisely in theboundary position of the OFDM symbol. The guard correlation/peakdetection circuit 12 detects the position where the guard correlationsignal has a peak, and outputs a value (peak timing value Np)identifying the timing of the peak position.

The peak timing value Np from the guard correlation/peak detectioncircuit 12 is supplied to the timing synchronization circuit 13, and thephase of the correlation value in the peak timing is supplied to thenarrow-band carrier-error calculation circuit 14.

The timing synchronization circuit 13 determines a start timing of FFTcalculation on the basis of a boundary position of the OFDM symbol,estimated by filtering, for example, the peak timing value Np from theguard correlation/peak detection circuit 12. The FFT-calculation starttiming is supplied as a start flag to the FFT calculation circuit 10.The FFT calculation circuit 10 will make FFT calculation by extracting asignal within the range of FFT calculation from the supplied OFDMtime-domain signal on the basis of the start flag. Also, the timingsynchronization circuit 13 calculates the amount of a phase rotationtaking place due to a time lag between the estimated boundary positionof the OFDM symbol and the timing in which the FFT calculation is to bestarted, generates a phase correction signal (complex signal) on thebasis of the calculated amount of phase rotation, and supplies the phasecorrection signal to the phase correction circuit 11.

The narrow-band carrier-error calculation circuit 14 calculates, basedon the phase of the correlation value in the boundary position of theOFDM symbol, a narrow-band carrier-frequency error component indicatinga narrow-band component of a shift of the center frequency used for thedigital orthogonal demodulation. More particularly, the narrow-bandcarrier-frequency error component is a shift of the center frequency,whose precision is less than ±½ of the frequency space of thesub-carrier. The narrow-band carrier-frequency error componentdetermined by the narrow-band carrier-error calculation circuit 14 issupplied to the addition circuit 16.

The wide-band carrier-error calculation circuit 15 calculates, based onthe OFDM frequency-domain signal from the phase correction circuit 11, anarrow-band carrier-frequency error component indicating a wide-bandcomponent of a shift of the center frequency used for the digitalorthogonal demodulation. The wide-band carrier-frequency error componentis a shift of the center frequency, whose precision is the sub-carrierfrequency space.

The wide-band carrier-frequency error component determined by thewideband carrier-error calculation circuit 15 is supplied to theaddition circuit 16.

The addition circuit 16 adds the narrow-band carrier-frequency errorcomponent calculated by the narrow-band carrier-error detection circuit14 and the wide-band carrier-frequency error component calculated by thewide-band carrier-error calculation circuit 15 to calculate a totalshift of the center frequency of the baseband OFDM signal supplied fromthe carrier-frequency error correction circuit 9. The addition circuit16 outputs the calculated total shift of the center frequency as afrequency error value. The frequency error value from the additioncircuit 16 is supplied to the NCO 17.

The NCO 17 is a so-called numerical-controlled oscillator, and generatesa carrier-frequency error correction signal of which the oscillationfrequency is increased or decreased correspondingly to the value of afrequency error from the addition circuit 16. The NCO 17 increases theoscillation frequency of a carrier-frequency error correction signalwhen the supplied frequency-error value is positive, and decreases theoscillation frequency when the supplied frequency-error value isnegative. The NCO 17 provides the above control to generate acarrier-frequency error correction signal of which the oscillationfrequency becomes stable when the frequency-error value is zero.

The frame synchronization circuit 18 detects a synchronization wordinserted in a predetermined position in an OFDM transmission frame todetect the start timing of the OFDM transmission frame. The framesynchronization circuit 18 identifies a symbol number assigned to eachOFDM symbol on the basis of the start timing of the OFDM transmissionframe, and supplies the symbol number to the equalization circuit 19etc.

The equalization circuit 19 makes a so-called equalization of the OFDMfrequency-domain signal. The equalization circuit 19 detects, based onthe symbol number supplied from the frame synchronization circuit 18, apilot signal called “scattered pilots (SP)” inserted in the OFDMfrequency-domain signal. The OFDM frequency-domain signal equalized bythe equalization circuit 19 is supplied to the demapping circuit 20.

The demapping circuit 20 makes a data demapping of the equalized OFDMfrequency-domain signal (complex signal), corresponding to the techniqueof demodulation such as QPSK, 16QAM or 64QAM, used for the OFDMfrequency-domain signal, to restore the transmission data. Thetransmission data from the demapping circuit 20 is supplied to thetransmission-channel decoding circuit 21.

The transmission-channel decoding circuit 21 makes transmission-channeldecoding of the supplied transmission data, corresponding to thebroadcasting method by which the transmission data has been broadcast.For example, the transmission-channel decoding circuit 21 makes a timedeinterleaving corresponding to a time-directional interleaving,frequency deinterleaving corresponding to a frequency-directionalinterleaving, deinterleaving corresponding to a bit interleaving fordistributing multi-valued symbol error, depucturing corresponding to apucturing for reduction of transmission bits, Viterbi decoding fordecoding a convolution-encoded bit string, deinterleaving in bytes,energy despreading corresponding to the energy spreading, errorcorrection corresponding to the RS (Reed-Solomon) coding, etc.

The transmission data having undergone the above transmission-channeldecoding is outputted as a transport stream defined in the MPEG-2Systems, for example.

The transmission-control information decoding circuit 22 decodestransmission-control information such as TMCC, TPS or the like,modulated in a predetermined position in the OFDM transmission frame.

Guard Correlation/Peak Detection Circuit

Next, the guard correlation/peak detection circuit 12 will beillustrated and described.

Note that constants Nu, Ng and Ns (natural numbers) will be used in thefollowing illustration and description. The constant Nu is the number ofsamples in one effective symbol. The constant Ng is the number ofsamples in the guard interval. For example, when the length of the guardinterval is ¼ of that of the effective symbol, Ng=Nu/4. The constant Nsis the number of samples in one OFDM symbol. That is, Ns=Nu+Ng.

FIG. 6 is a block diagram of the guard correlation/peak detectioncircuit 12, and FIG. 7 is a timing diagram of various signals in theguard correlation/peak detection circuit 12.

As shown in FIG. 6, the guard correlation/peak detection circuit 12includes a delay circuit 31, complex conjugate circuit 32,multiplication circuit 33, moving-sum circuit 34, amplitude calculationcircuit 35, angle conversion circuit 36, free-running counter 37, peakdetection circuit 38, and an output circuit 39.

The OFDM time-domain signal (see FIG. 7A) from the carrier-frequencyerror correction circuit 9 is supplied to the delay circuit 31 andmultiplication circuit 33. The delay circuit 31 is a shift registerformed from Nu register groups to delay the input OFDM time-domainsignal by the effective symbol time. The OFDM time-domain signal (seeFIG. 7B) delayed by the effective symbol by the delay circuit 31 issupplied to the complex conjugate circuit 32.

The complex conjugate circuit 32 calculates a complex conjugate of theOFDM time-domain signal delayed by the effective symbol time, andsupplies it to the multiplication circuit 33.

The multiplication circuit 33 multiplies the OFDM time-domain signal(see FIG. 7A) and the complex conjugate of the OFDM time-domain signaldelayed by the effective symbol time (see FIG. 7B) at every one sample.The result of the multiplication is supplied to the moving-sum circuit34.

The moving-sum circuit 34 includes a shift register formed for Ngregister groups and an adder to calculate a sum of values in theregisters, for example. For each of the Ng samples, it makes moving-sumcalculation of the results of multiplication sequentially supplied atevery one sample. The moving-sum circuit 34 will output a guardcorrelation signal (see FIG. 7C) indicating the correlation between theOFDM time-domain signal and the OFDM time-domain signal delayed by theeffective symbol (Nu samples). The guard correlation signal from themoving-sum circuit 34 is supplied to the amplitude calculation circuit35 and angle conversion circuit 36.

The amplitude calculation circuit 35 determines an amplitude componentof the guard correlation signal by squaring the real-number part andimaginary-number part, respectively, of the guard correlation signal,and adding the squares and calculating a square root of the result ofthe addition. The amplitude component of the guard correlation signal issupplied to the peak detection circuit 38.

The angle conversion circuit 36 determines a phase component of theguard correlation signal by making Tan−1 calculation of the real-numberpart and imaginary-number part of the guard correlation signal. Thephase component of the guard correlation signal is supplied to the peakdetection circuit 38.

The free-running counter 37 counts the operation clock. The count N ofthe free-running counter 37 is incremented in steps of one in a rangefrom 0 to Ns−1, and will return to zero when it exceeds Ns−1 (as in FIG.7D). That is to say, the free-running counter 37 is a cyclic counterwhose cycle is the number of samples (Ns) in the OFDM symbol period. Thecount N of the free-running counter 37 is supplied to the peak detectioncircuit 38.

The peak detection circuit 38 detects a point where the amplitude of theguard correlation signal is highest in one cycle (0 to Ns−1) of thefree-running counter 37, and detects a count at that point. When thecount of the free-running counter 37 shifts to a next cycle, the peakdetection circuit 38 will detect a new point where the guard correlationsignal has a high amplitude. The count detected by the peak detectioncircuit 38 is a peak timing Np indicative of a time at which the guardcorrelation signal attains its peak (peak time). Also, the peakdetection circuit 38 detects a phase component of the guard correlationsignal at the peak time, and supplies the detected phase component tothe output circuit 39.

The output circuit 39 takes in the count from the peak detection circuit38 and stores it into an internal register in a timing when the count Nof the free-running counter 37 becomes zero, and sets the count to astate in which is can be outputted to outside (see FIG. 7E). The countstored in the register is supplied as information indicative of the peaktime of the guard correlation signal (peak timing Np) to the timingsynchronization circuit 13 located downstream. Similarly, the outputcircuit 39 takes in the phase component from the peak detection circuit38 in a timing when the count N of the free-running counter 37 becomeszero, and stores it into the internal register, and sets the phasecomponent to a state in which it can be outputted to outside. The phasecomponent stored in the register is supplied to the narrow-bandcarrier-error calculation circuit 14 located downstream.

Also, the free-running counter 37 issues a validity flag that becomesHigh when the count N becomes zero (see FIG. 7F). The validity flagindicates a timing of issuing the peak timing Np and phase value to thedownstream circuit.

Note that although the guard correlation/peak detection circuit 12 isconstructed to generate the peak timing Np at each OFDM symbol, it maybe constructed to generate the peak timing Np at every M OFDM symbols (Mis a natural number), not at each OFDM symbol. In this case, however,the validity flag should be set to High (1) only once at every M OFDMsymbols.

Timing Synchronization Circuit

Next, the timing synchronization circuit 13 will be illustrated anddescribed.

The timing synchronization circuit 13 accurately synchronizes the OFDMsymbols with each other by canceling an error and fluctuation of thepeak timing Np caused in a multipath and fading environment.

FIG. 8 shows the internal construction of the timing synchronizationcircuit 13.

As shown in FIG. 8, the timing synchronization circuit 13 includes asymbol-boundary calculation circuit 43, symbol-boundary correctioncircuit 44, and a start-flag generation circuit 45.

The timing synchronization circuit 13 is supplied with the peak timingNp from the guard correlation/peak detection circuit 12 at every M OFDMsymbols (M is a natural number). Each circuit in the timingsynchronization circuit 13 has its operation controlled in an inputtiming of the peak timing Np (at every M OFDM symbols).

The symbol-boundary calculation circuit 43 filters the peak timing Npsupplied at every M OFDM symbols, and calculates a symbol-boundaryposition Nx indicative of the boundary position of the OFDM symbol. Thesymbol-boundary position Nx is represented by a range of 0 to Ns as acycle of the free-running counter 37 in the guard correlation/peakdetection circuit 12. However, the symbol-boundary position Nx has aprecision that is after the decimal point while the free-running counter37 and peak timing Np have a precision of an integer. Thesymbol-boundary calculation circuit 43 calculates a phase differencebetween an output (symbol-boundary position Nx) and input (peak timingNp), and filters it on the basis of the phase error component tostabilize the output (symbol-boundary position Nx).

The symbol-boundary position Nx from the symbol-boundary calculationcircuit 43 is supplied to the symbol-boundary correction circuit 44.

The symbol-boundary correction circuit 44 detects an integer componentof the symbol-boundary position Nx supplied at every M symbols, andcalculates a start time for the FFT calculation. The calculated starttime is supplied to the start-flag generation circuit 45. Also, thesymbol-boundary correction circuit 44 determines a time lag, whoseprecision is smaller than the operation-clock cycle, between thesymbol-boundary time and FFT-calculation start timing by detecting acomponent of the symbol-boundary position Nx, which is after the decimalpoint, and calculates, on the basis of the determined time lag, a phaserotation of a signal component included in each sub-carrier havingundergone the FFT calculation. The calculated phase rotation isconverted into a complex signal, and then supplied to the phasecorrection circuit 11.

The start-flag generation circuit 45 generates, based on the start timesupplied from the symbol-boundary correction circuit 44, a start flagwith which a timing of signal extraction (that is, an FFT-calculationstart timing) for the FFT calculation is identified. his start flag isgenerated at each OFDM symbol. It should be noted that the start flagmay be generated with a delay of a predetermined margin time from thesupplied symbol-boundary position Nx. However, the margin time shouldnever exceed at least the length of time of the guard interval. Bygenerating the start flag with a delay of the predetermined margin timefrom the symbol-boundary time as above, it is possible to cancel aninter-symbol interference caused by the detection of a preceding symbolboundary which is a ghost, for example.

Symbol-boundary Calculation Circuit

Next, the symbol-boundary calculation circuit 43 will be illustrated andexplained.

The symbol-boundary calculation circuit 43 is supplied with the peaktiming Np from the guard correlation/peak detection circuit 12, andestimates a symbol-boundary position Nx by making DLL (delay lockedloop) filtering on the basis of the peaking timing Np.

(Peak Timing Np, and Symbol-boundary Position Nx)

First, the peak timing Np and symbol-boundary position Nx will beexplained.

The peak timing Np indicates a peak position of the guard correlationsignal detected by the guard correlation/peak detection circuit 12, andthe symbol-boundary position Nx indicates a boundary position of theOFDM symbol of the received OFDM signal.

The peak timing Np and symbol-boundary position Nx take values,respectively, within a range of a value counted by the free-runningcounter 37 in the guard correlation/peak detection circuit 12. That is,each of the peak timing Np and symbol-boundary position Nx takes a valueranging from 0 to Ns. Since the peak timing Np is a count output fromthe free-running counter 37, so it takes a value ranging from 0 to Nswhose precision is an integer. The symbol-boundary position Nx is avalue ranging from 0 to Ns whose precision is after the decimal point aswell.

Since the free-running counter 37 in the guard correlation/peakdetection circuit 12 runs freely counting the operation clock for theOFDM receiver 1, so the count therefrom may be regarded as a referencetime for the OFDM receiver 1. Also, the count per cycle of thefree-running counter 37 is set to the number Ns of samples (sum of thenumber Nu of samples in the effective symbol and number Ng of samples inthe guard interval) in one symbol of the OFDM signal. Therefore, each ofthe peak timing Np and symbol-boundary position Nx represents a timesynchronous with the free-running counter 37. In other words, theyrepresent a phase relative to the symbol period of the OFDM signal.

Since in the OFDM receiver 1, a value within the range of the number Nsof samples in one symbol of the OFDM signal is used to generate a peaktiming Np and symbol-boundary position Nx, so it is possible to easilycontrol the synchronization of the symbol-boundary positions takingplace repeatedly.

(Internal Construction of the Symbol-boundary Calculation Circuit)

Next, the internal construction of the symbol-boundary calculationcircuit 43 will be described.

FIG. 9 is a circuit diagram of the symbol-boundary calculation circuit43.

As shown in FIG. 9, the symbol-boundary calculation circuit 43 includesa phase comparison circuit 51, limiter 52, asymmetric gain circuit 53,low-pass filter 54, clock-error correction circuit 55, phase generationcircuit 56, first register 58, second register 59, and a third register60.

The symbol-boundary calculation circuit 43 is supplied with the peaktiming Np and validity flag. The validity flag becomes High (1) at everyM symbols (M is a natural number) synchronously with the cyclic timingof the free-running counter 37. The symbol-boundary calculation circuit43 calculates a symbol-boundary position Nx in each timing when thevalidity flag becomes High.

(Phase Comparison Circuit)

FIG. 10 is a circuit diagram of the phase comparison circuit 51.

The phase comparison circuit 51 includes a subtracter 51 a and modulocalculator 51 b. The phase comparison circuit 51 is supplied with thepeak timing Np from the guard correlation/peak detection circuit 12, andalso with the symbol-boundary position Nx from the symbol-boundarycalculation circuit 43 by feedback. The symbol-boundary position Nxsupplied to the phase comparison circuit 51 is outputted from thesymbol-boundary calculation circuit 43 one sample before the inputtiming of the peak timing Np outputted from the guard correlation/peakdetection circuit 12 (namely, in the last timing when the validity flaghas become High).

The symbol-boundary position Nx is supplied to the phase comparisoncircuit 51 via the first register 58.

The subtracter 51 a subtracts the symbol-boundary position Nx from thepeak timing Np. The modulo calculator 51 b calculates the output fromthe subtracter 51 a to determine a subtraction residual per Ns (numberof samples from one symbol). That is, the modulo calculator 51 b dividesthe output from the subtracter 51 a by Ns (number of samples from onesymbol) to provide the residual of the division.

The phase comparison circuit 51 constructed as above calculates adifference Δθ between a symbol-boundary phase being currently estimatedand the peak phase of a current guard correlation signal on theassumption that the count of the free-running counter 37 is regarded asa symbol period. Namely, it calculates a difference between a currentestimated symbol-boundary time and the peak time of a current guardcorrelation signal on the assumption that the count of the free-runningcounter 37 is regarded as a reference time.

The phase difference Δθ calculated by the phase comparison circuit 51 issupplied to the limiter 52.

(Limiter)

FIG. 11 is a circuit diagram of the limiter 52.

The limiter 52 is supplied with the phase difference Δθ from the phasecomparison circuit 51. The limiter 52 includes a first comparator 52 ato make a comparison between an upper limit TH1 and phase difference Δθ,a second comparator 52 b to make a comparison between a lower limit TH2and phase difference Δθ, and a selector 52 c to select any one of thephase difference Δθ, upper value TH1 and lower value TH2. The relationin magnitude between the upper and lower limits TH1 and TH2 is TH1>TH2,The first comparator 52 a outputs Low (0) when the phase difference Δθis smaller than the upper limit TH1, or High (1) when the phasedifference Δθ is larger than the upper limit TH1. The second comparator52 b outputs Low (0) when the phase difference Δθ is larger than thelower limit TH2, or High (1) when the phase difference Δθ is smallerthan the lower limit TH2.

The selector 52 c outputs the phase difference Δθ from the phasecomparison circuit 51 as it is when the output from the first comparator52 a is Low (0) and output from the second comparator 52 b is Low (0).The selector 52 c outputs the upper limit TH1 when the output from thefirst comparator 52 a is High (1), and the lower limit TH2 when theoutput from the second comparator 52 b is High (1). Namely, the limiter52 outputs the phase difference Δθ as it is when the supplied phasedifference Δθ is between the upper and lower limits TH1 and TH2. Itclips the output with the upper limit TH1 when the supplied phasedifference Δθ is over the upper limit TH1, or with the lower limit TH2when the supplied phase difference Δθ is below the lower limit TH2.Thus, the limiter 52 limits the level of the phase difference Δθ withina range of TH1>TH2.

Note that since the phase difference Δθ varies in the positive- andnegative-going directions about “0”, so the limiter 52 sets the upperlimit TH1 to be equal to or larger than 0 and lower limit TH2 to smallerthan or equal to 0.

Because of this limiter 52, the symbol-boundary calculation circuit 43can cancel a large impulse noise caused in a fading environment, forexample, to improve the synchronization holding performance.

The phase difference Δθ whose level has been limited by the limiter 52is supplied to the asymmetric gain circuit 53.

(Asymmetric Gain Circuit)

FIG. 12 shows a circuit diagram of the asymmetric gain circuit 53.

The asymmetric gain circuit 53 is supplied with the phase difference Δθwhich is an output from the limiter 52 and has been limited in level.The asymmetric gain circuit 53 includes a comparator 53 a to determinethe polarity of the phase difference Δθ, a first multiplier 53 b tomultiply the phase difference Δθ by a first gain Ga, a second multiplier53 c to multiply the phase difference Δθ by a second gain Gb, and aselector 53 d to select an output from either the first or secondmultiplier 53 b or 53 c. The relation in magnitude between the first andsecond gains Ga and Gb is Ga>Gb.

The comparator 53 a compares the phase difference Δθ with 0, and outputsLow (0) when the phase difference Δθ<0 and High (1) when the phasedifference Δθ>0. The selector 53 d selects and outputs an output (aproduct of the phase difference Δθ and Ga) from the first multiplier 53b when the output from the comparator 53 a is Low (0), and an output(product of the phase difference Δθ and Gb) from the second comparator53 c when the output from the comparator 53 a is High (1).

That is, the asymmetric gain circuit 53 judges whether the peak timingNp is earlier or later than the symbol-boundary position Nx. When thejudgment is that the peak timing Np is earlier than the symbol-boundaryposition Nx, the asymmetric gain circuit 53 multiplies the phasedifference by a smaller gain (Gb). When the peak timing Np is later thanthe symbol-boundary position Nx, the asymmetric gain circuit 53multiplies the phase difference by a larger gain (Ga). Namely, in case aplurality of peak values is detected due to a multipath or the like, theasymmetric gain circuit 53 will multiply the phase difference Δθ by adifferent gain for synchronization with a temporarily earlier signal(main wave).

The phase difference Δθ multiplied by a gain by the asymmetric gaincircuit 53 is supplied to the low-pass filter 54.

(Low-pass Filter)

FIG. 13 is a circuit diagram of the low-pass filter 54.

The low-pass filter 54 is supplied with the phase difference Δθmultiplied by a gain by the asymmetric gain circuit 53 and validity flagfrom the guard correlation/peak detection circuit 12. The low-passfilter 54 includes an enable register 54 a, subtracter 54 b, multiplier54 c, and an adder 54 d.

The enable register 54 a is supplied at an enable port EN thereof withthe validity flag, and at an input port D thereof with the output (meanphase difference Ave Δθ) from the low-pass filter 54. The subtracter 54b subtracts an output from the register 54 a from the phase differenceΔθ from the asymmetric gain circuit 53. That is, the subtracter 54 bsubtracts the output (mean phase difference Ave Δθ) supplied from thelow-pass filter 54 from the supplied phase difference Δθ in a one-sampleearlier timing (the last timing in which the validity flag becomes High)to calculate a residual of the phase difference Δθ.

The multiplier 54 c multiplies the residual of the phase difference Δθfrom the subtracter 54 b by a predetermined coefficient K. The adder 54d adds the residual multiplied by the predetermined coefficient K andthe output from the register 54 a. The output from the adder 54 d is anoutput from the low-pass filter 54 (mean phase difference Ave Δθ).

That is, the low-pass filter 54 is an IIR type low-pass filter toaverage the supplied phase difference Δθ and calculate the mean phasedifference Ave Δθ.

The mean phase difference Ave Δθ calculated by the low-pass filter 54 issupplied to the clock-error correction circuit 55.

(Clock-error Correction Circuit)

FIG. 14 is a circuit diagram of the clock-error correction circuit 55.

The clock-error correction circuit 55 is supplied with the mean phasedifference Ave Δθ from the low-pass filter 54, and the validity flagfrom the guard correlation/peak detection circuit 12.

The clock-error correction circuit 55 includes a multiplier 55 a,register 55 b, first adder 55 c and a second adder 55 d.

The multiplier 55 a multiplies the mean phase difference Ave Δθ from thelow-pass filter 54 by a predetermined coefficient K1. The output fromthe multiplier 55 a represents a residual component resulted fromsubtraction of a clock-frequency error from a specific symbol beingprocessed from an estimated clock-frequency error. The residualcomponent of the clock-frequency error can be calculated with thecoefficient K1 being taken as a reciprocal of the number of samples forn samples (n is an interval of symbols for which the validity flag takesplace), for example, that is, as 1/(n×Ns).

The register 55 b stores a current estimated clock-frequency error. Theadder 55 c adds together the current estimated clock-frequency errorstored in the register 55 b and residual component from the multiplier55 a to calculate a new clock-frequency error.

The second adder 55 d adds the clock-frequency error from the firstadder 55 c to the mean phase difference Av Δθ from the low-pass filter54. The mean phase difference Ave Δθ having the clock-frequency erroradded thereto is supplied to the phase generation circuit 56.

The clock-error correction circuit 55 makes clock-frequency errorcorrection of the mean phase difference Ave Δθ by adding theclock-frequency error to the mean phase difference Ave Δθ as above.Thus, the symbol-boundary calculation circuit 43 can synchronize symbolswith an improved accuracy.

Note that the register 55 b is an enable register. The register 55 b issupplied at an enable port EN thereof with an input flag, and at aninput port D with the output from the first adder 55 c. Therefore, theregister 55 b stores an estimated clock-frequency error from the firstadder 55 c as a current estimated clock-frequency error.

The clock-frequency error can be calculated by cumulatively adding theresidual components of the clock-frequency error. That is, the outputfrom the multiplier 55 a is cumulatively added, and the cumulative sumis taken as an estimated clock-frequency error when it becomes stable.

Because of such a clock-error correction circuit 55 provided in thesymbol-boundary calculation circuit 43, the symbol boundary can becorrected using the clock-frequency error when calculating asymbol-boundary position. Thus, it is possible to calculate a symbolboundary more quickly and accurately.

(Phase Generation Circuit)

FIG. 15 is a circuit diagram of the phase generation circuit 56.

The phase generation circuit 56 is supplied with the mean phasedifference Ave Δθ after a clock-frequency error component from theclock-error correction circuit 55 is corrected and validity flag fromthe guard correlation/peak detection circuit 12.

The phase generation circuit 56 includes an adder 56 a and register 56b.

The register 56 b has a current estimated phase stored therein.

The adder 56 a is supplied with the mean phase difference Ave Δθ fromthe clock-error correction circuit 55, and current estimated phase fromthe register 56 b. The adder 56 a adds the mean phase difference Ave Δθand current estimated phase to provide a symbol-boundary position Nx.

The phase generation circuit 56 calculates a symbol-boundary position Nxby adding the current estimated phase to the mean phase difference AveΔθ. That is, the phase generation circuit 56 generates an output phase(symbol-boundary position Nx) indicating a final symbol-boundaryposition by adding a phase error component calculated on the path fromthe phase comparison circuit 51 to the clock-error correction circuit 55to the current estimated phase. It should be noted that since the outputphase (symbol-boundary position Nx) represents a phase of the period ofthe count (0 to Ns) generated by the free-running counter 37, so a valuemodulo-calculated with the count period (Ns) of the free-running counter37 when the calculated output phase is over Ns or under 0.

Note that the register 56 b is an enable register. The register 56 b issupplied at an enable port EN thereof with an input flag, and at aninput port D with the output from the first adder 56 a. Therefore, theregister 56 b stores an estimated output from the first adder 56 a as acurrent estimated phase. The current estimated phase can be calculatedby cumulatively adding the phase residuals of the estimated phase. Thatis, the output from the adder 56 a is cumulatively added, and thecumulative sum is taken as an estimated phase when it becomes stable.

Because of such a phase generation circuit 56 provided in thesymbol-boundary calculation circuit 43, the symbol boundary can becorrected using the current estimated phase when calculating asymbol-boundary position. Thus, it is possible to calculate a symbolboundary more quickly and accurately.

The symbol-boundary position Nx from the phase generation circuit 56 issupplied to the first and second registers 58 and 59.

(Output Circuit, and Feed-back Circuit)

Each of the first and second registers 58 and 59 of the symbol-boundarycalculation circuit 43 is an enable register.

The first register 58 is supplied at an enable portion EN thereof withthe validity flag, and at an input port D with the output(symbol-boundary position Nx) from the phase generation circuit 56. Thefirst register 58 is connected at the output port Q thereof to the phasecomparison circuit 51. Therefore, the first register 58 delays thesymbol-boundary position Nx by one sample (one effective symbol), andsupplies it to the phase comparison circuit 51.

The second register 59 is supplied at an enable port EN thereof with thevalidity flag, and at an input port D with the output (symbol-boundaryposition Nx) from the phase generation circuit 56. The second register59 is connected at an output port Q thereof to the symbol-boundarycorrection circuit 44. Therefore, the second register 59 delays thesymbol-boundary position Nx by one sample (one effective symbol), andsupplies it to the symbol-boundary correction circuit 44.

The third register 60 is a normal register which delays a signal inputto the input port D by one clock, and delivers it at the output port Q.The third register 60 is supplied at an input port D thereof with thevalidity flag from the guard correlation/peak detection circuit 12, andhas the output port Q thereof connected to the symbol-boundarycorrection circuit 44. Therefore, the third register 60 makes timingsynchronization with the symbol-boundary position Nx, and supplies avalidity flag to the symbol-boundary correction circuit 44.

Symbol-boundary Correction Circuit

Next, the symbol-boundary correction circuit 44 will be illustrated anddescribed.

FIG. 16 is a block diagram of the symbol-boundary correction circuit 44.

The symbol-boundary correction circuit 44 is supplied with thesymbol-boundary position Nx from the symbol-boundary calculation circuit43. The symbol-boundary position Nx has a value within the count cycle(0 to Ns) of the free-running counter 37 in the guard correlation/peakdetection circuit 12. That is, the symbol-boundary position Nx is avalue representing the symbol-boundary position of the PFDM signal by aphase relative to the period of the free-running counter 37. In otherwords, the symbol-boundary position Nx is a value represented by areference time generated by the free-running counter 37 when it isassumed that the reference time is generated by the free-running counter37.

Further, the symbol-boundary position Nx is filtered by theaforementioned symbol-boundary calculation circuit 43 to have theprecision thereof expressed to less than the operation-clock cycle ofthe free-running counter 37. Namely, the symbol-boundary position Nx isa value ranging from 0 to Ns whose precision includes a value after thedecimal point as well.

The symbol-boundary correction circuit 44 rewrites the symbol-boundaryposition Nx with an integer precision (that is the precision of theoperation-clock cycle) to calculate the symbol-boundary position withthe precision of the operation clock. Also, the symbol-boundarycorrection circuit 44 calculates a phase-error magnitude β_(m)indicating a difference in precision smaller than the operation-clockcycle between the FFT-extraction timing and symbol-boundary timing onthe basis of a precision, after the decimal point, of thesymbol-boundary position Nx, and generates a phase correction signal forsupply to the phase correction circuit 11 on the basis of thephase-error magnitude β_(m).

The symbol-boundary correction circuit 44 is internally constructed aswill be described below.

As shown in FIG. 16, the symbol-boundary correction circuit 44 includesan integral-rounding circuit 44 a, subtracter 44 b, phase-correctionamount calculation circuit 44 c, and a complex conversion circuit 44 d.

The integral-rounding circuit 44 a is supplied with the symbol-boundaryposition Nx calculated by the symbol-boundary calculation circuit 43.The integral-rounding circuit 44 a rounds the supplied symbol-boundaryposition Nx to the value of operation-clock precision. That is, itrounds the symbol-boundary position Nx to an integer included in a rangeof 0 to Ns. For example, the integral-rounding circuit 44 a makesintegral rounding such as rounding down the symbol-boundary position Nxto a value after the decimal point, rounding up the symbol-boundaryposition Nx to a value after the decimal point or rounding off thesymbol-boundary position Nx in relation to a value the decimal point.The integral-rounded symbol-boundary position Nx is supplied to thesubtracter 44 b. Further, the integral-rounded symbol-boundary positionNx is supplied as symbol-start information to the start-flag generationcircuit 45 as well.

The subtracter 44 b subtracts the symbol-boundary position Nx(integral-precision symbol-boundary position Nx) from theintegral-rounding circuit 44 a from the symbol-boundary position Nx(symbol-boundary position Nx expressed down to after the decimal point)from the symbol-boundary calculation circuit 43. The output from thesubtracter 44 b is a difference in a precision smaller than theoperation-clock cycle between the FFT-extraction timing andsymbol-boundary timing, that is, a phase-error magnitude β_(m). Thephase-error magnitude β_(m) from the subtracter 44 b is supplied to thephase-correction amount calculation circuit 44 c.

The phase-correction amount calculation circuit 44 c is supplied withthe phase-error magnitude β_(m) and the sub-carrier number n for eachsub-carrier as well. The sub-carrier number n is supplied from the framesynchronization circuit 18 or the like, for example. Thephase-correction amount calculation circuit 44 c calculates, from thephase-error magnitude β_(m), a correction amount θ_(clk)(n) for eachsub-carrier as given by the following equation:θ_(clk)(n)=2πnβ _(m) /N _(u)where n indicates a sub-carrier number, N_(u) indicates the number ofeffective symbols (that is, the number of sub-carriers).

FIG. 17 shows the arrangement of the sub-carriers of each frequency ofthe OFDM signal, and sub-carrier number, by way of example.

As shown in FIG. 17, the sub-carrier number n takes the number for asub-carrier positioned at the center frequency of the OFDM signal aszero (0) in this embodiment. Sub-carriers are positioned at intervals ofa frequency Δf (Δf=1/T:T is an effective symbol length) and a number isassigned to each of the sub-carriers. Sub-carriers positioned at lowerfrequencies than the center frequency are assigned numbers −1 to −512,respectively, while sub-carriers positioned at higher frequencies thanthe center frequency are assigned numbers 1 to 511, respectively. Thesub-carrier number n has a value corresponding to the frequency of thesub-carrier as shown in FIG. 17.

Also, the correction amount is different from one sub-carrier for thereason that since the phase-correction amount β_(m) is represented by adelay between the FFT-extraction timing and symbol-boundary timing, so aphase rotation taking place for the delay time is different from onefrequency to another.

As above, the phase-correction amount calculation circuit 44 cdetermines a phase-correction amount θ_(clk)(n) and supplies it to thecomplex conversion circuit 44 d.

The complex conversion circuit 44 d converts the suppliedphase-correction amount θ_(clk)(n) into a complex signal by calculatinga sine and cosine of the phase-correction amount θ_(clk)(n). The complexconversion circuit 44 d supplies the complex-converted phase-correctionamounts (cos (θ_(clk)(n)) and sin (θ_(clk)(n)) as phase-correctionsignals to the phase correction circuit 11.

Supplied with the phase-correction signals, the phase correction circuit11 makes complex multiplication of data corresponding to eachsub-carrier in the OFDM frequency-domain signal from the FFT calculationcircuit 10 by the phase-correction signals (cos (θ_(clk)(n)) and sin(θ_(clk)(n)) from the complex conversion circuit 44 d. Morespecifically, the phase correction circuit 11 makes a matrix calculationas follows:

$\;{\left( \frac{I_{out}(n)}{Q_{out}(n)} \right) = {\begin{pmatrix}{\cos\;{\theta_{clk}(n)}} & {{- \sin}\;{\theta_{clk}(n)}} \\{{\sin\;{\theta_{clk}(n)}}\mspace{14mu}} & {\cos\;{\theta_{clk}(n)}}\end{pmatrix}\left( \frac{I_{in}(n)}{Q_{in}(n)} \right)}}$where I_(in)(n) and Q_(in)(n) indicate results of calculation of thesub-carrier number n from the FFT calculation circuit 10, I_(in)(n)indicates a real part and Q_(in)(n) indicates an imaginary part, andI_(out)(n) and Q_(out)(n) indicate results of phase correction of thesub-carrier number n from the phase correction circuit 11. TheI_(out)(n) indicates a real-number component, and Q_(out)(n) indicatesan imaginary-number component.

Thus, the symbol-boundary correction circuit 44 has a very simplecircuit construction and can correct an error accurately. Further, sincethe symbol-boundary correction circuit 44 calculates an error amountusing a guard correlation/peak signal not yet FFT-calculated, so thesynchronization can be pulled in very fast than in case the correctionis made by feeding back a pilot signal or the like, for example.

Start-flag Generation Circuit

The start-flag generation circuit 45 is supplied with symbol startinformation (integrally-rounded symbol-boundary position Nx) supplied atevery M symbols from the symbol-boundary correction circuit 44, andgenerates a start flag indicative of a signal extraction timing for theFFT calculation (that is, an FFT-calculation start timing). A start flagis generated at each OFDM symbol.

As shown in FIG. 16, the start-flag generation circuit 45 includes acounter 45 a, register 45 b, and a comparator 45 c.

The counter 45 a is a same synchronization counter which operatessynchronously with the free-running counter 37 in the guardcorrelation/peak detection circuit 12. Namely, the counter 45 a countsvalues 0 to Ns. Further, the counter 45 a takes a phase delayed by adelay time in the aforementioned symbol-boundary calculation circuit 43from the count in the free-running counter 37.

The register 45 b stores the symbol start information(integrally-rounded symbol-boundary position Nx) from thesymbol-boundary correction circuit 44 each time a validity flag isasserted (timing “1”).

The comparator 45 c make a comparison between the count from the counter45 a and the symbol start information stored in the register 45 b togenerate a start flag that becomes High (1) in a timing of thecoincidence between the count and symbol start information.

The start flag generated by the comparator 45 c is supplied to the FFTcalculation circuit 10. The FFT calculation circuit 10 parallelizes asupplied serial data series in a timing in which the start flag hasbecome High (1) to extract Nu pieces of data for the FFT calculation.

As above, the start-flag generation circuit 45 converts a timingindicated by the symbol-boundary position Nx calculated by thesymbol-boundary calculation circuit 43 into a start flag synchronouswith the serial data series supplied to the FFT calculation circuit 10,and supplies it to the FFT calculation circuit 10.

Note that although the counter 45 a is provided in the start-flaggeneration circuit 45 according this embodiment, the count by thefree-running counter 37 may be adjusted by delaying and supplied to thecomparator 45 c.

Also, the delay of the counter 45 a in relation to the count by thefree-running counter 37 may be a value resulted from adding a margin toa processing delay of the symbol-boundary calculation circuit 43 toadjust the extraction range for the FFT calculation so that aninter-symbol interference due to a preceding ghost will be canceled.

In the foregoing, the present invention has been described in detailconcerning certain preferred embodiments thereof as examples withreference to the accompanying drawings. However, it should be understoodby those ordinarily skilled in the art that the present invention is notlimited to the embodiments but can be modified in various manners,constructed alternatively or embodied in various other forms withoutdeparting from the scope and spirit thereof as set forth and defined inthe appended claims.

1. A demodulator for demodulating an orthogonal frequency divisionmultiplex (OFDM) signal whose unit of transmission is a transmissionsymbol including effective symbols generated by performing time divisionof an information series and having modulating the information into aplurality of sub-carriers and a guard interval generated by copying asignal waveform of a part of the effective symbols, the demodulatorcomprising: a reference time generating circuit for generating areference time based on a reference clock signal; a Fourier transformcircuit for extracting a complex signal modulated in each sub-carrier ofthe transmission symbol by extracting signal areas corresponding to thenumber of the plurality of sub-carriers for the effective symbols of theOFDM signal sampled with the reference clock signal and performing aFourier transform of the extracted signal areas; a guard correlationpeak time detecting circuit for detecting a timing in which anautocorrelation of the guard interval portion of the OFDM signal attainsa peak and for generating a peak time synchronous with the referencetime; a symbol-boundary time estimating circuit for estimating, based onthe peak time, a symbol-boundary time that is a boundary time of thetransmission symbol synchronous with the reference time; a timingcontrol circuit for controlling a timing position where the complexsignal is extracted by the Fourier transform circuit based on thesymbol-boundary time representing a precision of the reference clocksignal cycle; and a phase correcting circuit for calculating aphase-correction amount based on the symbol-boundary time representing aprecision smaller than the reference clock signal cycle and making,based on the calculated phase-correction amount, phase correction of thecomplex signal having been modulated in each of the plurality ofsub-carriers and extracted by the Fourier transform circuit.
 2. Theapparatus according to claim 1, wherein: the timing control circuitrounds the symbol-boundary time to the precision of the reference clocksignal and controls an extraction timing position of a signal area bythe Fourier transform circuit based on the rounded symbol-boundary time;and the phase correcting circuit calculates a difference between asymbol-boundary time estimated by the symbol-boundary time estimatingcircuit and the symbol-boundary time rounded by the timing controlcircuit and calculates the phase correction amount based on the basis ofthe calculated time difference.
 3. The apparatus according to claim 1,wherein the phase correcting circuit calculates the phase correctionamount for each sub-carrier of the plurality of sub-carrierscorresponding to a symbol-boundary time represented by a precisionsmaller than an operation clock cycle and the frequency of eachsub-carrier in which a complex signal for the phase correction ismodulated.